The formation of various integrated circuit (IC) structures on a wafer often relies on lithographic processes, sometimes referred to as photolithography, or simply lithography. For instance, patterns can be formed from a photo resist layer by passing light energy through a mask (or reticle) having an arrangement to image the desired pattern onto the photo resist layer. As a result, the pattern is transferred to the photo resist layer. In areas where the photo resist is sufficiently exposed and after a development cycle, the photo resist material can become soluble such that it can be removed to selectively expose an underlying layer (e.g., a semiconductor layer, a metal or metal containing layer, a dielectric layer, etc.). Portions of the photo resist layer not exposed to a threshold amount of light energy will not be removed and serve to protect the underlying layer. The exposed portions of the underlying layer can then be etched (e.g., by using a chemical wet etch or a dry reactive ion etch (RIE)) such that the pattern formed from the photo resist layer is transferred to the underlying layer. Alternatively, the photo resist layer can be used to block dopant implantation into the protected portions of the underlying layer or to retard reaction of the protected portions of the underlying layer. Thereafter, the remaining portions of the photo resist layer can be stripped.
There is a pervasive trend in the art of IC fabrication to increase the density with which various structures are arranged. As a result, there is a corresponding need to increase the resolution capability of lithography systems. One promising alternative to conventional optical lithography is a next-generation lithographic technique known as extreme ultraviolet (EUV) lithography where wavelengths in the range of about 11 nm to about 14 nm are used to expose the photo resist layer. For example, using a numerical aperture of about 0.25, a wavelength of about 13.4 nm and a k1 value of about 0.6, it has been proposed that a resolution of about 32 nm can be achieved.
However, attempts to implement EUV lithography have encountered a number of challenges. For example, mask non-flatness can result in unacceptable overlay errors. As is known in the art, overlay relates the lateral positioning between layers comprising an integrated circuit. If the layers are not properly aligned with each other, the performance of the devices of the integrated circuit can be compromised. In this situation, it is likely that the integrated circuit, if not the entire wafer (upon which multiple integrated circuits may be fabricated), may be unusable.
Accordingly, there exists a need in the art for techniques and systems for monitoring EUV lithography mask flatness.